1. Field of the Invention
The present invention relates to a method for forming a metal interconnection in a semiconductor device. More particularly, the present invention relates to an edge bead removal process for a copper metal interconnection.
2. Description of the Related Art
Semiconductor manufacturing processes are mainly classified into a front end of the line (FEOL) process for forming a transistor on a silicon substrate, and a back end of the line (BEOL) process for forming metal interconnections. The BEOL process refers to a process of forming power supply and signal transfer paths on a silicon substrate to connect transistors to each other so as to constitute integrated circuits.
Copper (Cu), which is a material having high EM (Electro-migration) tolerance, has been mainly used for such a BEOL process. However, since the copper (Cu) is not easily etched, but is oxidized during the interconnection process, it is difficult to pattern the copper (Cu) by employing a typical photo process technology.
In order to form a copper metal interconnection, a dual damascene process technology has been developed as an alternative plane of the photo technology. The dual damascene process is to form a via and a trench in an inter-layer dielectric layer formed on a semiconductor substrate, fill the via and trench with copper (Cu) through an electro-chemical plating (ECP) scheme, and then planarize the upper surface of a semiconductor substrate through a chemical mechanical polishing (CMP) process.
Meanwhile, if an edge part of a wafer is not properly treated during the BEOL process in which a metal process and an insulating layer forming process are repeated, defects may occur on the wafer in following processes. Accordingly, after performing the ECP process, an edge bead removal (EBR) process is performed to remove a copper plating layer formed in the edge part of the wafer by using a predetermined chemical agent. If the wafer is not subject to the EBR process, an unnecessary copper plating layer formed in the edge part of the wafer (an edge part, in which a pattern is not formed, is generally called a bevel area) may be released during the following process. In addition, since the released copper residue deteriorates equipment for following processes, the yield rate and the performance of the semiconductor device may be degraded.
However, since there is no special tester capable of determining whether the EBR process is normally performed, the next process is directly performed without a special test after performing the EBR process. Accordingly, if the density of the chemical agent used in the EBR process is abnormal, or if the EBR process is not normally performed due to the fail of the equipment or the mistake of a worker, a portion of the unnecessary copper layer may remain in the edge part of the wafer. Accordingly, since the following processes are performed with respect to the wafer having a defect, the yield rate and the performance of a semiconductor device may be degraded.